In recent years, semiconductor integrated circuits such as LSIs (Large Scale Integration) are progressing with finer design rules and greater densities. For example, hierarchical design is common as a layout design method of semiconductor integrated circuits. In the hierarchical design, for example, a circuit divided into a plurality of blocks in accordance with their functions is layered, and layout design is performed by a plurality of designers, respectively, for the layers. Data of the layout designs are subsequently collected for the entire layout design.
Moreover, as described above, in semiconductor integrated circuits, a distance between signal lines is becoming shorter with finer design rules and greater densities. Therefore, the influence of crosstalk noise between signal lines on a semiconductor integrated circuit is becoming stronger, and there are various technologies for suppressing the influence of crosstalk noise. For example, there is a technology for shielding crosstalk noise by inserting a power line around a signal line (in eight directions), or by inserting a power line running parallel between two signal lines in a semiconductor integrated circuit.    Patent Document 1: International Publication Pamphlet No. WO 2007/077623    Patent Document 2: Japanese Laid-open Patent Publication No. 2004-186257
However, in the above technology, a power line is inserted to shield crosstalk noise, which may decrease the degree of freedom in layout, and there are also some places where insertion is difficult. Moreover, there are also some power lines that are difficult to be inserted, such as global power lines arranged in a grid (mesh) pattern. Furthermore, it is difficult to realize parallel arrangement of a power line in order to perform shielding for a massive number of lines.
In other words, if the above technology for inserting a power line is applied to a semiconductor integrated circuit, it is difficult to realize parallel arrangement of a power line for all lines, and in reality parts where a power line runs parallel and parts where the power line does not run parallel are mixed.
Here, in a crosstalk noise check on a semiconductor integrated circuit having both parts where a power line runs parallel and where the power line does not run parallel, an effect of a power line suppressing crosstalk noise is ignored even if there exists the part where the power line runs parallel. In other words, a crosstalk noise value is calculated assuming that crosstalk noise is not suppressed by the power line, and the crosstalk noise value is compared with a predetermined limiting value to perform an error determination. In this manner, examples of reasons why the suppression of crosstalk noise by a power line is ignored include, for example, that a process is performed at high speeds. As described above, the suppression of crosstalk noise by a power line is ignored. Accordingly, a crosstalk noise value to be calculated in a crosstalk noise check becomes larger than an actual value. Therefore, the number of error determinations increases in such a crosstalk noise check. In this case, the layout design of a semiconductor integrated circuit has a problem that the load of the layout design is heavy since work such as the extension of a distance between lines is performed at every error determination.